Efficiently manage rule exploration, definition and validation, ensuring that engineering intent is fully achieved. But what happens if you miss or skip over a problem with a non-critical net? Simple problems can go undetected until late in the design cycle causing timely and costly re-spins. Typical design practice guidelines advise engineers and designers to reserve signal integrity simulation for high risk nets only. We’ve entered a time where our devices – with their increasing fast data rates and edge rates – are causing almost every signal in their PCB to behave like transmission lines.
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